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(R)
ISL6210
Data Sheet November 28, 2006 FN6392.0
PRELIMINARY
Dual Synchronous Rectified MOSFET Drivers
The ISL6210 integrates two ISL6208A drivers and is optimized to drive two independent power channels in a synchronous-rectified buck converter topology. These drivers combined with an Intersil ISL62xx multiphase PWM controller forms a complete single-stage core-voltage regulator solution with high efficiency performance at high switching frequency for advanced microprocessors. The IC is biased by a single low voltage supply (5V), minimizing driver switching losses in high MOSFET gate capacitance and high switching frequency applications. Each driver is capable of driving a 3nF load with less than 10ns rise/fall time. Bootstrapping of the upper gate driver is implemented via an internal low forward drop diode, reducing implementation cost, complexity, and allowing the use of higher performance, cost effective N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously. The ISL6210 features 4A typical sink current for the lower gate driver, enhancing the lower MOSFET gate hold-down capability during PHASE node rising edge, preventing power loss caused by the self turn-on of the lower MOSFET due to the high dV/dt of the switching node. The ISL6210 also features an input that recognizes a highimpedance state, working together with Intersil multiphase PWM controllers to prevent negative transients on the controlled output voltage when operation is suspended. This feature eliminates the need for the schottky diode that may be utilized in a power system to protect the load from negative output voltage damage.
Features
* 5V Quad N-Channel MOSFET Drives for Two Synchronous Rectified Bridges * Adaptive Shoot-Through Protection - Active Gate Threshold Monitoring - Programmable Dead-Time * 0.4 On-Resistance and 4A Sink Current Capability * Supports High Switching Frequency - Fast Output Rise and Fall - Ultra Low Three-State Hold-Off Time (20ns) * Low VF Internal Bootstrap Diode * Low Bias Supply Current * Power-On Reset * QFN Package - Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat No Leads-Product Outline - Near Chip-Scale Package Footprint; Improves PCB Efficiency and Thinner in Profile * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Core Voltage Supplies for Intel(R) and AMD(R) Microprocessors * High Frequency Low Profile High Efficiency DC/DC Converters * High Current Low Voltage DC/DC Converters * Synchronous Rectification for Isolated Power Supplies
Ordering Information
PART NUMBER (Note) ISL6210CRZ PART MARKING TEMP. RANGE (C) PACKAGE (Pb-Free) PKG. DWG. #
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Technical Brief 400 and Technical Brief 417 for Power Train Design, Layout Guidelines, and Feedback Compensation Design * Technical Brief 447 "Guidelines for Preventing Boot-toPhase Stress on Half-Bridge MOSFET Driver ICs"
62 10CRZ -10 to +100 16 Ld 4x4 QFN L16.4x4
ISL6210CRZ-T 62 10CRZ -10 to +100 16 Ld 4x4 QFN L16.4x4 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved. Intel(R) is a registered trademark of Intel Corporation. AMD(R) is a registered trademark of Advanced Micro Devices, Inc. All other trademarks mentioned are the property of their respective owners.
ISL6210 Pinout
ISL6210 (16 LD 4X4 QFN) TOP VIEW
PHASE1 13 12 UGATE1 11 BOOT1 GND PVCC 3 FCCM 4 5 PGND 6 LGATE2 7 EN 8 PHASE2 10 BOOT2 9 UGATE2 PWM2 PWM1 15
16 GND 1 LGATE1 2
Block Diagram
ISL6210
EN PVCC FCCM BOOT1 UGATE1
VCC SHOOTTHROUGH PROTECTION PHASE1
VCC 14
CHANNEL 1
4.25K PWM1 4K
PVCC
LGATE1 PGND
VCC
CONTROL LOGIC
PGND BOOT2 UGATE2
PVCC
4.25K PWM2 4K GND SHOOTTHROUGH PROTECTION
PHASE2
CHANNEL 2
PVCC
LGATE2 PGND PAD
THE PAD ON THE BOTTOM SIDE OF THE QFN PACKAGE MUST BE SOLDERED TO THE CIRCUIT'S GROUND.
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FN6392.0 November 28, 2006
ISL6210 Typical Application - Multiphase Converter Using ISL6210 Gate Drivers
+5V
BOOT1
+12V
UGATE1 VCC PHASE1 FCCM EN DUAL DRIVER ISL6210 LGATE1 PVCC +5V BOOT2 +12V
+5V FB VSEN COMP VCC ISEN1 PGOOD EN PWM1 PWM2 MAIN ISEN2 CONTROL ISL62xx PWM1 PWM2
UGATE2 PHASE2
PAD GND
LGATE2
VID
PGND
+VCORE ISEN3 FCCM PWM3 PWM4 GND ISEN4 UGATE1 VCC PHASE1 +5V BOOT1
+12V
FCCM DUAL DRIVER ISL6210
LGATE1
PVCC +5V BOOT2 +12V
EN
UGATE2 PWM1 PWM2 LGATE2 PAD GND PGND PHASE2
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ISL6210
Absolute Maximum Ratings
Supply Voltage (PVCC, VCC) . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Input Voltage (VEN, VPWM) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V BOOT Voltage (VBOOT-GND). . . -0.3V to 33V (DC) or 36V (<200ns) BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . -0.3V to 7V (DC) -0.3V to 9V (<10ns) PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 30V (DC) GND -8V (<20ns Pulse Width, 10J) UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT VPHASE - 5V (<20ns Pulse Width, 10J) to VBOOT LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V GND - 2.5V (<20ns Pulse Width, 5J) to VCC + 0.3V Ambient Temperature Range . . . . . . . . . . . . . . . . . .-40C to +125C HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Thermal Information
Thermal Resistance (Notes 1 and 2) JA(C/W) JC(C/W) QFN Package . . . . . . . . . . . . . . . . . . 46 8.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . .-10C to +100C Maximum Operating Junction Temperature . . . . . . . . . . . . . +125C Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10%
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. 2. JC, "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER SUPPLY CURRENT Bias Supply Current POWER-ON RESET POR Rising POR Falling Hysteresis BOOTSTRAP DIODE Forward Voltage Drop PWM INPUT Sinking Impedance Source Impedance Three-State Rising Threshold Three-State Falling Threshold
These specifications apply for TA = -10C to +100C, Unless Otherwise Noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS A
IVCC
PWM pin floating, VVCC = 5V
-
170
-
2.6 -
3.4 3.0 400
4.2 -
V V mV
VF RPWM_SNK RPWM_SRC
VVCC = 5V, forward bias current = 2mA
0.3
0.60
0.7
V
8.0 8.3 VVCC = 5V VVCC = 5V 1.08 3.4 -
10.4 10.6 1.3 3.65 80 20
15 25 1.5 3.98 -
k k V V ns ns
Three-State Shutdown Holdoff Time Three-state to UG/LG Rising Propagation Delay SWITCHING TIME (See Figure 1) UGATE Rise Time (Note 3) LGATE Rise Time (Note 3) UGATE Fall Time (Note 3) LGATE Fall Time (Note 3) UGATE Turn-Off Propagation Delay LGATE Turn-Off Propagation Delay UGATE Turn-On Propagation Delay LGATE Turn-On Propagation Delay
tTSSHD tPTS
tPDLU or tPDLL + Gate Falling Time
tRU tRL tFU tFL tPDLU tPDLL tPDHU tPDHL
VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, Outputs Unloaded VVCC = 5V, Outputs Unloaded VVCC = 5V, Outputs Unloaded; RSET = 0 VVCC = 5V, Outputs Unloaded; RSET = 0
-
8.0 8.0 8.0 4.0 20 27 26 26
-
ns ns ns ns ns ns ns ns
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ISL6210
Electrical Specifications
PARAMETER UGATE Turn-On Propagation Delay LGATE Turn-On Propagation Delay Minimum LGATE On Time in DCM (Note 3) OUTPUT Upper Drive Source Resistance (Note 3) Upper Drive Source Current (Note 3) Upper Drive Sink Resistance (Note 3) Upper Drive Sink Current (Note 3) Lower Drive Source Resistance (Note 3) Lower Drive Source Current (Note 3) Lower Drive Sink Resistance (Note 3) Lower Drive Sink Current (Note 3) NOTE: 3. Guaranteed by Characterization. Not 100% tested in production. RUG_SRC IUG_SCR RUG_SNK IUG_SNK RLG_SRC ILG_SCR RLG_SNK ILG_SNK 250mA Source Current VUGATE-PHASE = 2.5V 250mA Sink Current VUGATE-PHASE = 2.5V 250mA Source Current VLGATE = 2.5V 250mA Sink Current VLGATE = 2.5V 1.0 2.00 1.0 2.00 1.0 2.00 0.4 4.00 2.5 2.5 2.5 1.0 A A A A These specifications apply for TA = -10C to +100C, Unless Otherwise Noted (Continued) SYMBOL tPDHU tPDHL tLGMIN TEST CONDITIONS VVCC = 5V, Outputs Unloaded; RSET = 80k VVCC = 5V, Outputs Unloaded; RSET = 80k MIN TYP 41 33 400 MAX UNITS ns ns ns
Functional Pin Description
NUMBER 1 2 3 4 5 6 7 8 9 10 NAME GND LGATE1 PVCC FCCM PGND LGATE2 EN FUNCTION Bias and reference ground. All signals are referenced to this node. Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET. This pin supplies power to both the lower and higher gate drives in ISL6614. Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND. Logic control input that will force continuous conduction mode (HIGH state) or allow discontinuous conduction mode (LOW state). Placing a series resistor in this input will allow the switching dead-time to be programmed. It is the power ground return of both low gate drivers. Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET. Logic control input that will enable (HIGH state) or disable (LOW state) the IC. Shutdown current is <1A.
PHASE2 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This pin provides a return path for the upper gate drive. UGATE2 Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET. BOOT2 Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this pin and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value. Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this pin and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
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BOOT1
12 13 14 15 16 N/A
UGATE1 Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET. PHASE1 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This pin provides a return path for the upper gate drive. VCC PWM1 PWM2 PAD Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic capacitor from this pin to GND. The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during operation, see the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller. The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during operation, see the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller. Connect this pad to the power ground plane (GND) via thermally enhanced connection.
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ISL6210 Timing Diagram
2.5V PWM tPDHU tPDLU tRU tPTS 1V UGATE tRU tTSSHD
tFU
LGATE 1V tRL tTSSHD tPDLL tPDHL tFL
tPTS
FIGURE 1. TIMING DIAGRAM
Description
Theory of Operation
Designed for speed, the ISL6210 dual MOSFET driver controls both high-side and low-side N-Channel FETs for two separate channels of a Multiphase PWM system from two independent PWM signals. A rising edge on PWM initiates the turn-off of the lower MOSFET (see Timing Diagram). After a short propagation delay [tPDLL], the lower gate begins to fall. Typical fall times [tFL] are provided in the Electrical Specifications section. Adaptive shoot-through circuitry monitors the LGATE voltage. When LGATE has fallen below 1V, UGATE is allowed to turn ON. This prevents both the lower and upper MOSFETs from conducting simultaneously, or shootthrough. A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [tPDLU] is encountered before the upper gate begins to fall [tFU]. The upper MOSFET gate-to-source voltage is monitored, and the lower gate is allowed to rise after the upper MOSFET gate-to-source voltage drops below 1V. The lower gate then rises [tRL], turning on the lower MOSFET. This driver is optimized for converters with large step down compared to the upper MOSFET because the lower MOSFET conducts for a much longer time in a switching period. The lower gate driver is therefore sized much larger to meet this application requirement. The 0.5 on-resistance and 4A sink current capability enable the lower gate driver to absorb the current injected to
the lower gate through the drain-to-gate capacitor of the lower MOSFET and prevent a shoot through caused by the high dv/dt of the phase node.
Diode Emulation
Diode emulation allows for higher converter efficiency under light-load situations. With diode emulation active, the ISL6210 will detect the zero current crossing of the output inductor and turn off LGATE. This ensures that discontinuous conduction mode (DCM) is achieved. Diode emulation is asynchronous to the PWM signal. Therefore, the ISL6210 will respond to the FCCM input immediately after it changes state.
NOTE: Intersil does not recommend Diode Emulation use with rDS(ON) current sensing topologies. The turn-OFF of the low side MOSFET can cause gross current measurement inaccuracies.
Three-State PWM Input
A unique feature of the ISL6210 and other Intersil drivers is the addition of a shutdown window to the PWM input. If the PWM signal enters and remains within the shutdown window for a set holdoff time, the output drivers are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. Otherwise, the PWM rising and falling thresholds outlined in the ELECTRICAL SPECIFICATIONS determine when the lower and upper gates are enabled.
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection to prevent upper and lower MOSFETs from conducting simultaneously and shorting the input supply. This is accomplished by ensuring the falling gate has turned off one MOSFET before the other is allowed to turn on.
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ISL6210
During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a 1V threshold, at which time the UGATE is released to rise. Adaptive shoot-through circuitry monitors the upper MOSFET gate-to-source voltage during UGATE turn-off. Once the upper MOSFET gate-to-source voltage has dropped below a threshold of 1V, the LGATE is allowed to rise. In addition to gate threshold monitoring, a programmable delay between MOSFET switching can be accomplished by placing a resistor in series with the FCCM input. This delay allows for maximum design flexibility over MOSFET selection. The delay can be programmed from 5ns to 50ns and is obtained from the absolute value of the current flowing into the FCCM pin. If no resistor is used, the minimum 5ns delay is selected. Gate threshold monitoring is not affected by the addition or removal of the additional dead-time. Refer to Figure 2 and Figure 3 for more detail.
FCCM = VCC or GND 50 45 40 DEAD-TIME (ns) 35 30 25 20 15 10 5 0 0 167 333 500 RDELAY (k) 667 833 1000 tDELAY
FIGURE 3. ISL6210 PROGRAMMABLE DEAD-TIME vs DELAY RESISTOR
GATE B
GATE A
The equation governing the dead-time seen in Figure 3 is expressed as:
T DELAY ( ns ) = [ 0.045 x R DELAY ( k ) ] + 5ns (EQ. 1)
ADAPTIVE SHOOT-THROUGH PROTECTION 1V
The equation can be rewritten to solve for RDELAY as follows:
( T DELAY ( ns ) - 5ns ) R DELAY ( k ) = -----------------------------------------------------0.045 (EQ. 2)
Internal Bootstrap Diode
FCCM = RESISTOR to VCC or GND GATE A GATE B
This driver features an internal bootstrap diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The following equation helps select a proper bootstrap capacitor size:
Q GATE C BOOT_CAP ------------------------------------V BOOT_CAP Q G1 * PVCC Q GATE = ----------------------------------- * N Q1 V GS1
ADAPTIVE PROTECTION WITH DELAY
(EQ. 3)
TDELAY = 5n - 50ns 1V
FIGURE 2. PROGRAMMABLE DEAD-TIME
where QG1 is the amount of gate charge per upper MOSFET at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The VBOOT_CAP term is defined as the allowable droop in the rail of the upper gate drive. As an example, suppose two IRLR7821 FETs are chosen as the upper MOSFETs. The gate charge, QG, from the data sheet is 10nC at 4.5V (VGS) gate-source voltage. Then the QGATE is calculated to be 22nC at PVCC level. We will assume a 200mV droop in drive voltage over the PWM cycle. We find that a bootstrap capacitance of at least 0.110F is required. The next larger standard value
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ISL6210
capacitance is 0.22F. A good quality ceramic capacitor is recommended.
2.0 1.8 1.6 CBOOT_CAP (F) 1.4 1.2 1.0 0.8 0.6
nC 50
where the gate charge (QG1 and QG2) is defined at a particular gate to source voltage (VGS1and VGS2) in the corresponding MOSFET data sheet; IQ is the driver's total quiescent current with no load at both drive outputs; NQ1 and NQ2 are number of upper and lower MOSFETs, respectively. The IQ VCC product is the quiescent power of the driver without capacitive load and is typically negligible. The total gate drive power losses are dissipated among the resistive components along the transition path. The drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (RG1 and RG2, should be a short to avoid interfering with the operation shoot-through protection circuitry) and the internal gate resistors (RGI1 and RGI2) of MOSFETs. Figures 5 and 6 show the typical upper and lower gate drives turn-on transition path. The power dissipation on the driver can be roughly estimated as:
P DR = P DR_UP + P DR_LOW + I Q * VCC R LO1 R HI1 P Qg_Q1 P DR_UP = -------------------------------------- + --------------------------------------- * --------------------R HI1 + R EXT1 R LO1 + R EXT1 2 R LO2 R HI2 P Qg_Q2 P DR_LOW = -------------------------------------- + --------------------------------------- * --------------------R HI2 + R EXT2 R LO2 + R EXT2 2 R GI1 R EXT2 = R G1 + ------------N
Q1
QGATE = 100nC
0.4 0.2 20nC
0.0 0.0
0.1
0.2
0.3
0.4 0.5 0.6 0.7 VBOOT_CAP (V)
0.8
0.9
1.0
FIGURE 4. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
(EQ. 6)
Power Dissipation
Package power dissipation is mainly a function of the switching frequency (FSW), the output drive impedance, the external gate resistance, and the selected MOSFET's internal gate resistance and total gate charge. Calculating the power dissipation in the driver for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of 125C. The maximum allowable IC power dissipation for the SO14 package is approximately 1W at room temperature, while the power dissipation capacity in the QFN packages, with an exposed heat escape pad, is around 2W. See Layout Considerations paragraph for thermal transfer improvement suggestions. When designing the driver into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses due to the gate charge of MOSFETs and the driver's internal circuitry and their corresponding average driver current can be estimated with Equations 4 and 5, respectively,
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q * VCC Q G1 * PVCC 2 P Qg_Q1 = -------------------------------------- * F SW * N Q1 V GS1 Q G2 P Qg_Q2 = -------------------------------------- * F SW * N Q2 V GS2 Q G1 * N Q1 Q G2 * N Q2 I DR = ----------------------------- + ----------------------------- * F SW + I Q V GS2 V GS1 * PVCC 2 (EQ. 4)
R GI2 R EXT2 = R G2 + ------------N
Q2
PVCC
BOOT D CGD RHI1 RLO1 G RG1 RGI1 CGS S PHASE Q1 CDS
UGATE
FIGURE 5. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC D CGD RHI2 RLO2 LGATE G RG2 RGI2 CGS GND S Q2 CDS
(EQ. 5) FIGURE 6. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
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FN6392.0 November 28, 2006
ISL6210 Layout Considerations
Reducing Phase Ring
The parasitic inductances of the PCB and the power devices (both upper and lower FETs) could cause serious ringing, exceeding absolute maximum rating of the devices. The negative ringing at the edges of the PHASE node could add charges to the bootstrap capacitor through the internal bootstrap diode, in some cases, it could cause over stress across BOOT and PHASE pins. Therefore, user should do a careful layout and select proper MOSFETs and drivers. The D2PAK and DPAK package MOSFETs have high parasitic lead inductance, which can exacerbate this issue. FET selection plays an important role in reducing PHASE ring. If higher inductance FETs must be used, a Schottky diode is recommended across the lower MOSFET to clamp negative PHASE ring. A good layout would help reduce the ringing on the phase and gate nodes significantly: * Avoid uses via for decoupling components across BOOT and PHASE pins and in between VCC and GND pins. The decoupling loop should be short. * All power traces (UGATE, PHASE, LGATE, GND, VCC) should be short and wide, and avoid using via; otherwise, use two vias for interconnection when possible. * Keep SOURCE of upper FET and DRAIN of lower FET as close as thermally possible. * Keep connection in between SOURCE of lower FET and power ground wide and short. * Input capacitors should be placed as close to the DRAIN of upper FET and SOURCE of lower FETs as thermally possible.
NOTE: Refer to Intersil Tech Brief TB447 for more information.
Thermal Management
For maximum thermal performance in high current, high switching frequency applications, connecting the thermal pad of the QFN part to the power ground with multiple vias is recommended. This heat spreading allows the part to achieve its full thermal potential.
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FN6392.0 November 28, 2006
ISL6210 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.50 1.95 1.95 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.65 BSC 0.60 16 4 4 0.60 12 0.75 0.15 2.25 2.25 0.35 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 5 5/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN6392.0 November 28, 2006

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